Scaling intracranial neural interfaces to thousands of channels while maintaining power dissipation below 20 milliwatts requires radical circuit innovations. This paper outlines sub-threshold amplifier operation, asynchronous event-driven ADC architectures, and near-threshold logic pipelines evaluated in pre-clinical animal models.
Operating input transistors in weak inversion maximizes the transconductance-to-current ratio (gm/Id), enabling 1024 recording amplifiers to draw less than 4.2 milliwatts of total analog power.
Instead of sampling continuously at 20 kHz, level-crossing ADCs sleep until neural potentials deviate by a preset threshold, slashing active data rates by 80% during neural quiescence.